The invention described herein relates generally to semiconductor devices and processing. In particular, the invention relates to methods of semiconductor processing that can be used to form variable thickness gates without inducing excessive damage in shallow trench isolation (STI) regions of a semiconductor surface.
The semiconductor industry uses a number of different methods to construct CMOS circuit devices on semiconductor surfaces. In some architectures, it is beneficial to form gate layers having several different thicknesses. One approach is described as a xe2x80x9cgrowetch-growxe2x80x9d (GEG) process which is used to create gate layers having different thicknesses. Such GEG processes require numerous masking and etching steps. Consequently, these processes are very time intensive. Additionally, GEG processes require numerous surface cleaning steps that can seriously erode the semiconductor surface.
In other embodiments, gate layers can be formed having different thicknesses simultaneously. This is commonly accomplished by treating the different gate regions of the semiconductor surface with a range of active materials. The type and dose of the implanted active materials can be used to either retard or accelerate oxide formation in the various gate regions, thereby facilitating the formation of gate oxide layers having differing thicknesses.
FIGS. 1-4 illustrate a conventional approach for such simultaneous gate formation. In FIG. 1 a semiconductor substrate 100 is provided. Such a substrate can be formed of a variety of semiconductor materials including, but not limited to, silicon and doped silicon. The substrate 100 is formed in a configuration suitable for having integrated circuit (IC) structures formed thereon. In the depicted embodiment, the substrate 100 is provided having a pattern of shallow trench isolation (STI) structures 101 formed thereon. The pattern of STI structures 101 is configured such that IC devices (e.g., CMOS structures or other semiconductor electronic devices) can be formed on the substrate 100.
Commonly, STI structures 101 are formed by etching isolation trenches in the substrate surface and the depositing silicon dioxide (SiO2) to complete the isolation structure 101. Additionally, the surface of the substrate is provided with a xe2x80x9csacrificial oxidexe2x80x9d layer 102 which protects the underlying substrate surface. Commonly, the sacrificial oxide layer 102 is formed by thermally oxidizing the silicon of the substrate 100 to form a SiO2 sacrificial oxide layer 102. Typically, the sacrificial oxide layer 102 is formed to a thickness of about 100-150 xc3x85 thick.
FIG. 2 depicts a next step, wherein the substrate 100 is masked with a photoresist layer 110. Typically, the photoresist layer 110 includes a pattern of openings 111 that correspond to an underlying gate oxide region 112. The photoresist layer 110 masks portions of the substrate 100. The opening 111 formed in the photoresist layer 110 includes some degree of error tolerance to account for misalignments during processing. As a result, portions 113 of the STI structure 101 are not covered by the photoresist layer 110 and are exposed to subsequent process steps.
FIG. 3 depicts the continuation of the foregoing conventional process. The substrate surface is then implanted with ions 115. In the regions covered with the photoresist layer 110 (like regions x and y), the implanted ions are blocked. Whereas, in the regions defined by openings, the ions 115 penetrate into an ion implantation region 120 (indicated with the dashed line). The ion implantation region 120 includes exposed portions of the sacrificial oxide layer 102, the substrate 100, and trench 101 (identified herein as the now implanted regions of the sacrificial oxide layer 102xe2x80x2 and trench 101xe2x80x2). The purpose of such ion implantation is to change the oxidation properties of the silicon regions 112 (also referred to as gate oxide regions, where the gate oxide layers will be grown. By carefully and controllably dosing the substrate with appropriate implantation material (or not), many different thicknesses of gate oxide layers can be formed simultaneously during a subsequent thermal oxidation process. For example, implantation with nitrogen retards the subsequent rate of oxide formation in the substrate. Conversely, implantation with fluorine accelerates the rate of oxide formation. Thus, under the same thermal oxidation conditions and process times, SiO2 layers of different thickness can be formed on the same substrate. The advantages of such a process are numerous and obvious.
Unfortunately, one of the drawbacks of this process is that the implantation process that introduces active materials into the gate oxide region 112 also implants other regions of the surface. As previously indicated, the sacrificial oxide layer 102xe2x80x2 and trench 101xe2x80x2 are also implanted. Such implantation results in significant damage to the indicated portions of the sacrificial oxide layer 102xe2x80x2 and the trench 101xe2x80x2. The importance of this damage is discussed in the following paragraphs.
In order to create the gate oxide layer in the gate oxide region 112, the substrate 100 must be thermally processed in an oxidation furnace. However, to accomplish oxidation, the photoresist layer 110 and the sacrificial oxide layer 102 are commonly removed from the surface. Thus, the photoresist layer 110 is removed and the sacrificial oxide layer 102, 102xe2x80x2 is also removed. Therein lies one of the shortcomings of existing processes. Commonly, the sacrificial oxide layer 102 is removed using a cleaning process that involves immersion and rinsing in an etch bath formed of HF and de-ionized water (DI).
Because the sacrificial oxide layer 102xe2x80x2 and trench 101xe2x80x2 have been damaged by the implantation process, they etch at a significantly higher etch rate than the unimplanted portions of the surface (such as region y).
FIG. 4 shows the results of a typical HF surface cleaning process after the surface has been subjected to conventional ion implantation. Because of the damage caused in the implantation region 120, the implanted portions of the isolation trench 101xe2x80x2 and the implanted portions of the sacrificial oxide layer 102xe2x80x2 are eroded more rapidly than the unimplanted portions of the surface (such as the unimplanted sacrificial oxide layer 102 and the unimplanted trench region y). Consequently, the implanted portions of the surface (e.g., 101xe2x80x2, 102xe2x80x2) have etch rates on the order of three to four times the etch rates of the unimplanted regions (such as y and 102). This presents certain difficulties because the entire unimplanted sacrificial oxide layer 102 must be removed. The amount of cleaning (etching) time required to remove unimplanted sacrificial oxide layer 102 is much greater than that required for the implanted regions. Thus, as the unimplanted sacrificial oxide layer 102 is removed, substantial amounts of material are removed from the implanted regions (e.g., 101xe2x80x2, 102xe2x80x2). In fact, for each given amount of material removed from the undamaged sacrificial oxide layer 102, three to four times as much implanted material is removed. The implanted material in the trench 101xe2x80x2 is etched at a much faster rate than the adjacent unimplanted material y. As a result, extremely uneven etch profiles similar to that depicted in FIG. 4 are created during cleaning. In a typical example, using a 30:1 DI:HF cleaning solution, when 100 xc3x85 of a sacrificial oxide layer 102 is removed, about 300-400 xc3x85 of implanted grown SiO2 material 101xe2x80x2 and about 120 xc3x85 of unimplanted grown SiO2 material 101 is removed from the isolation trench. This non-uniform etch profile in the isolation trench results in a number of electrical defects that can result in circuit failure in the fabricated electronic circuitry.
Many other approaches have been tried to reduce the level of material removed from the trench. In one example, the aforementioned GEG processes are used. But, as is known to those having ordinary skill in the art, such processes require many additional process steps and suffer from excessive surface erosion. Another approach is to reduce the exposure to HF cleaning solutions. This entails, among other things, a significant reduction in sacrificial oxide thickness. Unfortunately, this can result in reduced gate quality and increased defect density. For these and other reasons, an improved process resulting in less damage to layers of the semiconductor surface is desired.
In accordance with the principles of the present invention, a method of blanket ion implanting a semiconductor substrate surface to induce uniform damage over selected portions of the surface thereby reducing non-uniform etch effects caused by the varying etch rates of surface materials and conditions during surface cleaning is disclosed.
Embodiments of the invention include a method for removing sacrificial oxide layers from a semiconductor substrate surface. The method includes providing a semiconductor substrate having gate oxide regions and a sacrificial oxide layer of a predetermined thickness formed thereon. The surface of the substrate is pattern masked to reveal openings in the gate oxide regions and ion implanted through the openings in the pattern mask to form gate oxide regions. The pattern mask is removed from the substrate and a blanket implantation of the sacrificial oxide layer is performed. The substrate is cleaned to remove the sacrificial oxide layer and the substrate is left in readiness for further processing. In another related embodiment, the blanket ion implantation is performed prior to pattern masking.
Another embodiment of the invention comprises a method for forming gate layers on a semiconductor substrate surface. A semiconductor substrate suitable for forming electronic circuitry thereon is provided. The substrate includes gate regions and a sacrificial oxide layer of a predetermined thickness formed thereon. The substrate is masked with a pattern mask that includes openings in the gate regions. High energy ions are implanted into the gate regions through the openings in the pattern mask. The pattern mask is removed from the substrate and a low energy blanket ion implantation of the surface is conducted. The substrate is cleaned to remove the sacrificial oxide layer and gate oxide layers are then formed in the gate oxide regions. The substrate is now in readiness for further processing as needed.
These and other aspects of the present invention are described in the detailed description of the embodiments set forth hereinbelow.